A semiconductor chip contains an array of devices whose contacts are interconnected by patterns of conductive wires. In order to take full advantage of the device and the circuit density on a given chip, it is usually necessary to make interconnections among the various devices and circuit elements in the chip. However, due to the level of integration of devices and circuits on a chip, interconnections can no longer be made by means of a single level network of conductive lines. Often, it is necessary to form two or more such levels of conductive lines which are vertically spaced apart and separated by intermediate insulating layers.
Connections can be made between the different levels of conductive lines by means of vias which are etched through the insulating layer separating the levels. These vias are filled with a metal to form via studs. These multiple levels of conductor wiring interconnection patterns, with the individual levels connected by via studs, operate to distribute signals among the circuits on the chip.
In its simplest form, a via may be made by first masking an insulating layer with a photoresist and then selectively etching a portion of the insulating layer. The via is etched through an opening formed in the photoresist using well known photolithographic techniques to form an opening to the underlying conductive layer. Depending on the aspect ratio and the interconnection ground rules, isotropic or anisotropic etching processes may be used to form a hole in the dielectric.
After via etching, and photoresist removal, it is essential to deposit a conductive layer in the via. This deposited conductive layer forms an electrical interconnection between the conductive layers of the device. However, a liner or barrier layer is usually desirable between the insulative and conductive layers.
The presence of a liner layer on the sidewalls on the via is desirable because it enhances the structural integrity of the entire laminate. A good liner or barrier film effectively isolates the conductive metal from the dielectric as well as adhering firmly to the conductive metal and the dielectric. However, the best liner materials tend to be more resistive, as compared to conductive materials, so the presence of the liner at the bottom of the via increases the contact resistance of the structure. An increase in contact resistance is not desirable because it may lead to slower propagation of electrical signals through the wiring structure. For structural integrity, the liner should line the entire sidewall and will generally cover the bottom of the via as well.
Materials capable of forming a liner layer generally have a higher resistance than conductive materials. Liner materials have generally been selected to simultaneously minimize contact resistance, provide adequate adhesion between insulative and conductive materials, and provide a good diffusion barrier.
The contact resistance problem is compounded when copper, Cu, is used as the conductive metal. When Cu is used, the presence of a continuous dissimilar liner material with comparatively higher resistivity at the bottom of the via deters the fabrication of a single crystalline, or continuous, interface between the via conductor material and the wiring level below.
The formation of a single crystalline or polycrystalline interface in wiring structures is advantageous since it provides greater structural integrity for the interface between the via and the wiring level below. In the prior art, after via definition over a metal line, typically a continuous liner or barrier film is deposited on the sidewalls and bottom of the via. This is then followed with seed layer deposition over the liner. Finally, the via is filled with a metal using a suitable deposition method such as electroplating, CVD, electroless deposition or PVD techniques. In prior art wiring structures, the vias and lines are separated by a liner film; therefore an interface exists between the vias and the lines of the wiring structure.
A typical prior art wiring structure is shown in FIGS. 1(a)-(b). Specifically, FIG. 1(a) shows a typical via level 50 on a planarized metal level 52. Via 50 consists of an opening in the dielectric that is landed on metal level 52. The prior art via structure comprises a continuous liner layer 50c, a seed layer 50b and a conductive metal 50a. An interlevel dielectric 54 separates via level 50 from metal level 52. After metal planarization, a plane of the liner layer 50c remains at the interface of the via and the trench.
In view of the drawbacks mentioned hereinabove, there remains a need of fabricating semiconductor devices which contain a continuous, single crystalline or polycrystalline conductive material, particularly Cu, between the various wiring levels of the semiconductor device.